28th May 2018      
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PowerQUICC II (Design 2)

Designed using the PowerQUICC II, from Motorola and operating at 66MHz, this board contains FLASH, SDRAM and Serial EEPROM memory, an 8-bit Utopia port, an interrupt controller implemented in a Xilinx CPLD, Ethernet Phy, battery backed RTC, Serial RS232 and isolated parallel I/O signals for telecom switching. Interfaces to a proprietary backlane used a further Xilinx CPLD to control both synchronous and asychronous ATM peripherals. During the design, careful consideration was given to both EMC and ESD to ensure simplified compliance testing.
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Qutec Systems Ltd.
Registered Office: The Old Church, Verulam Road St. Albans, Herts. AL3 4DH
Registration No. 1807115