PowerQUICC II (Design 2)

Designed using the PowerQUICC II, from Motorola and operating at 66MHz, this board contains FLASH, SDRAM and Serial EEPROM memory, an 8-bit Utopia port, an interrupt controller implemented in a Xilinx CPLD, Ethernet Phy, battery backed RTC, Serial RS232 and isolated parallel I/O signals for telecom switching. Interfaces to a proprietary backlane used a further Xilinx CPLD to control both synchronous and asychronous ATM peripherals. During the design, careful consideration was given to both EMC and ESD to ensure simplified compliance testing.